1. Field of the Invention
The present invention relates to an SPDT (single pole double throw) switch, and a communication unit using the same. More particularly, the present invention relates to an SPDT switch for use in a mobile communication unit as an antenna switch, and to a communication unit using the same.
2. Description of the Related Art
Recent demands to reduce the size and cost of mobile communication units require that single pole double throw (SPDT) switches used as antenna switches be reduced in size and cost. An SPDT switch is a switch having three terminals, one of which is connectable to either of the other two terminals.
FIG. 7 is a circuit diagram showing a conventional SPDT switch disclosed in Japanese Unexamined Patent Application Publication No. 9-23101.
Referring to FIG. 7, an SPDT switch 1 includes a first terminal P1, a second terminal P2, a common terminal P3, a first field-effect transistor (FET) Q1, a second FET Q2, a first inductor L1, a second inductor L2, resistors R1, R2, and R3, a first control terminal P4, a second control terminal P5, and a third control terminal P6. The source of the first FET Q1 is connected to the first terminal Pl, and the source of the second FET Q2 is connected to the second terminal P2. The drain of the first FET Q1 and the drain of the second FET Q2 are connected to each other, and are connected to the common terminal P3. The first inductor L1 is connected across the drain and source of the first FET Q1, and the second inductor L2 is connected across the drain and source of the second FET Q2. The gate of the first FET Q1 is connected to the first control terminal P4 via the resistor R1, and the gate of the second FET Q2 is connected to the second control terminal P5 via the resistor R2. The drain of the first FET Q1 and the drain of the second FET Q2 are connected to the third control terminal P6 via the resistor R3. Each of the first FET Q1 and the second FET Q2 has a pinch-off voltage set at xe2x88x920.5 V. Symbol xe2x80x9cDxe2x80x9d in FIG. 7 represents the drain.
In the SPDT switch 1 having such a construction, potentials of 0 V, 0 V, and xe2x88x923 V are applied to the first control terminal P4, the second control terminal P5, and the third control terminal P6, respectively. Then, the first FET Q1 has a potential of 0 V at the drain and source, and the gate-drain (or gate-source) voltage is 0 V, thereby turning on the first FET Q1. The second FET Q2 also has a potential of 0 V at the drain and source, and the gate-drain (or gate-source) voltage is xe2x88x923 V, which is less than the pinch-off voltage, thus turning off the second FET Q2. In the off state, the second FET Q2 has an off-capacitance across the drain and source. The inductance of the second inductor L2 is set so that the second inductor L2 may form a parallel resonance with the off-capacitance of the second FET Q2 having a resonant frequency synchronous with the frequency of an undesired signal. In theory, infinite impedance is thus obtained across the drain and source of the second FET Q2 at the frequency of such an undesired signal. Therefore, an electrical connection is established between the first terminal P1 and the common terminal P3 via the first FET Q1, and no electrical connection occurs between the second terminal P2 and the common terminal P3 because infinite impedance is obtained at the parallel resonance between the off-capacitance of the second FET Q2 and the second inductor L2.
On the other hand, suppose that potentials of xe2x88x923 V, 0 V, and 0 V are applied to the first control terminal P4, the second control terminal P5, and the third control terminal P6, respectively. In contrast to the previous description, an electrical connection between the second terminal P2 and the common terminal P3 is established via the second FET Q2, and no electrical connection occurs between the first terminal P1 and the common terminal P3 because infinite impedance is obtained by the parallel resonance between the off-capacitance of the first FET Q1 and the first inductor L1.
The SPDT switch 1 therefore allows either one of the first terminal P1 and the second terminal P2 to be electrically connected to the common terminal P3 by changing the voltages to be applied to the first control terminal P4 and to the second control terminal P5.
However, the SPDT switch 1 shown in FIG. 7 is disadvantageous in that two potentials of 0 V and xe2x88x923 V must be alternately applied to the first control terminal P4 and the second control terminal P5. In other words, while 0 V or xe2x88x923 V is applied to the first control terminal P4, xe2x88x923 V or 0 V must be simultaneously applied to the second control terminal P5. Specifically, two control lines adapted to change the potentials to be applied to the respective terminals are required, or otherwise, a single control line branched into two and configured so that either signal may be inverted is required.
In such cases, an increased area may be required for such a control line(s). Otherwise, an extra control port such as a CPU (central processing unit) or logic for allowing a control signal to be inverted may be required, thus, making it difficult to reduce the size and cost of the switch.
Accordingly, the present invention provides an SPDT switch which can be easily controlled and which is compact, and a communication unit using the same.
To this end, in an aspect of the present invention, an SPDT switch includes first and second terminals, and first and second FETs with Schottky connection gates. The drain of the first FET and the source of the second FET are connected to the first terminal and the second terminal, respectively, and the source of the first FET and the drain of the second FET are connected to the common terminal. A fixed potential xcex3 is applied to the gate of the second FET, and one of potentials xcex1 and xcex2 is applied to the gate of the first FET, where xcex1 less than xcex3 less than xcex2, to allow one of the first and second terminals to be electrically connected to the common terminal. The pinch-off voltage Vp1 of the first FET is set to satisfy 0 greater than Vp1 greater than xcex1xe2x88x92xcex3, and the pinch-off voltage Vp2 of the second FET is set to satisfy 0 greater than Vp2 greater than xcex3xe2x88x92xcex2.
The SPDT switch may further include a first inductor connected in parallel to the first FET, and a second inductor connected in parallel to the second FET1.
The SPDT switch may further include a first inductor connected in series to the first FET, a first capacitor connected in parallel to the series connection of the first FET and the first inductor, a second inductor connected in series to the second FET, and a second capacitor connected in parallel to the series connection of the second FET and the second inductor.
The SPDT switch may further include a third FET with a Schottky connection gate, having a pinch-off voltage Vp3 set to satisfy 0 greater than Vp3 greater than xcex3xe2x88x92xcex2, and a fourth FET with a Schottky connection gate, having a pinch-off voltage Vp4 set to satisfy 0 greater than Vp4 greater than xcex1xe2x88x92xcex3. The third FET may have a drain connected to the drain of the first FET, a source connected to ground via a first ground capacitor, and a gate connected to the gate of the second FET. The fourth FET may have a drain connected to the source of the second FET, and a source connected to ground via a second ground capacitor, and a gate connected to the gate of the first FET.
In another aspect of the present invention, a communication unit contains an SPDT switch such as that described above.
An SPDT switch embodied by the present invention can be easily controlled and reduced in size and cost. Furthermore, a communication unit using such an SPDT switch can also be reduced in size and cost.